1. Field of the Invention
The present invention relates to asynchronous transfer mode (ATM) communications, and is suitable for cell transmission over wireless links. More specifically, the present invention relates to a technique for improving cell transfer delay and cell delay variation. Although the present invention has been developed for utilization in wireless communication, it is widely applicable to wired and other common communication systems.
In this specification, "cell delay variation" is defined as including the transfer delay between a source and a destination, and the variation in this transfer delay.
2. Description of Related Art
In view of the mobility offered by wireless communication systems, wireless ATM has recently been attracting attention. The aim of wireless ATM is to achieve a mobile communication service which provides seamless multimedia services by carrying out ATM cell transmission using wireless communication systems and integrating this with wired ATM communication systems based on optical fiber. To realize high frequency utilization efficiency, wireless ATM extracts only valid cells which contain significant information and transmits only these cells over wireless links.
A single ATM terminal generally has a plurality of connections, and different transmission quality characteristics, i.e., qualities of service (QoS), can be required by each connection. In general, there are stringent requirements on cell delay variation in Constant Bit Rate and Variable Bit Rate techniques, and on cell loss in Available Bit Rate and Unspecified Bit Rate techniques. In addition, the cell rate of ABR and UBR frequently fluctuates dynamically with time.
In FIG. 12, which serves to explain the allocation of bandwidth or time slots, time is plotted along the horizontal axis and cell rate along the vertical axis. In ATM communication systems, transmission speed (number of cells/second) is generally defined in terms of a peak value (the peak cell rate) and an average value (the average cell rate) for each connection. A difference between the peak and the average values means that the transmission speed is fluctuating. Similarly, a permissible cell delay variation (in seconds) is provided for each connection. A quality class, therefore, has to be provided in correspondence with each of these quality requirements, and bandwidth or time slots have to be allocated to each quality class.
However, if too many quality classes are provided, control of the quality class in the network becomes complicated. Studies are currently being made of classifying cell delay variation, for example, into a class for which a cell delay variation of 3 ms or less is required, and a class for which there is no required value for cell delay variation. Transmission speed will also generally fluctuate in connection with a quality class for which there is no required value for cell delay variation.
An explanation will be given here of the case where there are two quality classes for cell delay variation. Namely, it will be assumed that there are the following two quality classes: quality class 1 in which a high quality is required for cell delay variation, and quality class 2 in which there are no quality requirements for cell delay variation. Letting the total of the maximum cell rates (number of cells/second) for connections of quality class 1 be R1, the total of the average cell rates for connections of quality class 2 be R2, and the total of the maximum cell rates for connections of quality class 2 be R3, time slots or bandwidth will be allocated in accordance with a transmission cell rate equivalent to the sum of cell rates R1 and R4, where R2.ltoreq.R4.ltoreq.R3. If R4 is set to R3, then although it will be possible to transfer ATM cells with a small cell delay variation irrespective of quality class, there will be a large bandwidth or time slot requirement. On the other hand, if R4 is set to R2, then efficient use can be made of time slots or bandwidth, and in a wireless ATM system, in particular, efficient use can be made of frequency. However, if the transmission cell rate fluctuates in connections of quality class 2, connections of quality class 1 will also experience cell delay variation with a resultant deterioration of quality.
In FIG. 13, which shows the relation between input cells 50 and output cells 52 in a prior art example, 15 time slots 54 are provided in every period T, and there is a mixture of cells of quality class 1 (56) and quality class 2 (58) and idle cells 59 (if necessary). In addition, there are 6 time slots 60 provided in each period T in the transmission path 62 between the input and the output. When there are few quality class 2 cells, the quality class 1 cells are output without delay. However, when there is a rapid increase in quality class 2 cells, these cells intrude in the transmission timing of the quality class 1 cells, with the result that delay occurs. In the example of FIG. 13, it is assumed that both quality class 1 and quality class 2 have an average cell rate of 3 cells/T.
In FIG. 14, which is a block diagram of a prior art system, transmitter TX comprises valid cell extractor 91 for eliminating idle cells from the input cells and extracting valid cells, transmission buffer 92, in which extracted cells are stored in order to absorb any fluctuation in their cell rate, and transmitting circuit 93 which transmits only the valid cells at a fixed rate. Valid cells are identified by comparing the virtual path identifier (VPI) and/or the virtual channel identifier (VCI), contained in the cell header, with the fixed VPI and/or VCI showing an idle cell, and detecting when these do not match.
In receiver RX, cells received by receiving circuit 94 are output in accordance with the transmission speed of the connections. The simplest method of doing this is to provide a first-in-first-out (FIFO) memory 96.sub.1 -96.sub.n for each connection, i.e., for each VPI and/or VCI, and to have a leaky bucket scheme which reads these FIFO memories in accordance with the average cell rate of each connection. A FIFO read control method is the so-called round robin scheme which accesses FIFO memories 96.sub.1 -96.sub.n in turn, outputs a cell if there is one to be read, and reads the next FIFO memory if there is not. If a round robin scheme is employed, receiver RX comprises cell demultiplexer 95 which demultiplexes cells into the various connections in accordance with the VPI and/or VCI; n FIFO memories 96.sub.1 -96.sub.n each of which stores these cells; and FIFO read controller 97 for controlling the reading of these FIFO memories 96.sub.1 -96.sub.n. The cell reading rate of FIFO read controller 97 depends on the interface speed with the terminal or network, and the transmission speed between transmitter and receiver is either the same as or lower than the interface speed.
In the prior art, a separate FIFO memory is required for each connection and each FIFO memory has to have a capacity according to the maximum transmission speed allowed for the connection. For this reason, FIFO memories with very large capacities are required on the receiving side, which results in an increased hardware requirement.
One method of reducing the hardware requirement would be not to have a FIFO memory for each connection but instead to have a common memory and employ some form of address control for this memory. However, the memory address control would be extremely complex and difficult to implement. Furthermore, in all of these methods, because a memory corresponding to a connection with no quality requirement for cell delay variation will sometimes be read before a memory corresponding to a connection with stringent quality requirements for cell delay variation, the cell delay variation of this latter type of connection will sometimes increase.
The cell rate of a connection with no quality requirement for cell delay variation frequently fluctuates. Therefore, if a cell rate larger than the average cell rate R2 shown in FIG. 12 is input, transmission of cells for a connection with a stringent quality requirement for cell delay variation will be delayed, and the cell delay variation will be increased. This could be remedied if the buffer capacity of the receiver was increased or the average transfer delay was made larger, but the buffer capacity required for the FIFO memories would then become larger still.